Currently, most computers adopt Neumann type architecture in which a program is stored in a storage similar to ordinary data, and the program is read from the storage and is executed. Generally, a Neumann type computer is realized as a computer system which includes a computer comprising a processor such as a CPU (Central Processing Unit) for controlling execution of the program and a main storage for temporarily storing the program or the data, I/O (input/output) devices for performing I/O operation, an auxiliary (secondary) storage for storing the program or the data for a long period of time, and the like.
When the program is executed under control of the processor, an instruction such as "operation" or "transfer" contained in the program is read from the main storage, and instruction processing such as operation or transmission of a control signal for directing each part of the computer to perform a transfer process or the like according to the instruction is carried out. The processor includes a program counter for specifying areas in the main storage where instructions to be executed are stored, an instruction register for storing the instructions, and the like. In principle, the processor sequentially reads the instructions and performs instruction processing.
As an example of a technique employed in the processor to realize high-speed processing, there is "pipeline processing". As described above, basically, the instructions are sequentially read and executed. In the processor, processing is performed in plural stages, including instruction fetch, instruction decoding, instruction execution, outputting operation results, and the like. In the pipeline processing, processing in each stage is carried out in parallel to realize high-speed processing. In sequential processing, until an instruction is subjected to processing in plural stages, processing of a subsequent instruction cannot be started, whereas in the pipeline processing, processing of the subsequent instruction starts without waiting for a completion of the processing of the instructions, which enables high-speed processing. For this reason, most processors recently used adopt pipeline processing.
To be more detailed, in the pipeline processing, an instruction is fetched, and then a subsequent instruction is fetched while performing processing for the fetched instruction in subsequent stages, which processing is called a "prefetch process". Hence, the processor has a storage area for the instruction under execution and a storage area for the instruction to be prefetched. The instruction to be prefetched is basically determined according to the order of the instructions contained in the program. When the instructions are sequentially prefetched, there is a possibility that the pipeline processing cannot be performed appropriately when "jump" or "branch" is included in the program. In order to perform the prefetch process appropriately, a branch prediction method has been developed.
By the way, various interruptions often occur in the computer system. One important role of the processor is to control processing for these interruptions. The interruption occurs when a request is issued from the peripheral device such as the I/O device or when incorrect processing is performed during execution of the program, and demands that it should be processed with priority even if a specified program is being executed. When the interruption occurs, the processing (program) under execution is interrupted and another processing responding to the interruption is performed. This is called interruption processing.
When a timer or an external device issues an interruption request signal to the processor or when an interruption request is issued during execution of the program, the processor temporarily saves the program under execution and then executes a processing program in response to the interruption request signal. Upon completion of interruption processing, the processor resumes execution of the program from when it was interrupted.
FIG. 7 is a control (execution) flow diagram for explaining control for the interruption processing performed by a general processor according to a prior art. The same figure shows storage state of the main storage which has areas 701-703. The area 701 contains a procedure (program) for interruption processing, the area 702 contains a procedure for performing processing for a specified cause of the interruption, and the area 703 contains a general program such as an application program. The procedure stored in the area 701 includes analyzing the cause of the interruption. The storage area in the main storage are uniquely specified by addresses.
The same figure also shows how the general processor according to the prior art performs control when the interruption occurs while an instruction is contained in the general program is processed. In this case, the processor carries out the procedure for interruption processing in a specified area in the main storage to analyze the cause of the interruption, and then it performs processing for the cause of the interruption.
As shown in FIG. 7, when the interruption occurs while the instruction 1a stored in an area specified by an address n is executed, in control flow P701, the processor executes an instruction 2a stored in an area specified by an address AAAA indicating the head of the area 701. Then, in control flow P702a, the processor executes an instruction 2b, and then sequentially executes the following instructions. As a result of this, the processor analyzes the cause of the interruption at the point of an instruction 2k, and thereby obtains a starting address of an area which contains the procedure for performing processing for the cause of the interruption. In this case, this procedure is stored in an area starting at an address XXXX. In control flow P702b, the processor executes an instruction 3a stored in the area located at the address XXXX, and sequentially executes the following instructions.
FIG. 8 is a timing chart showing the state of the prior art processor which performs such processing. In the figure, there are shown instruction addresses indicating where instructions to be executed are stored and instructions under execution at respective timings.
At timing t0, the address n indicating the storage area for the instruction 1a is obtained as the instruction address and the instruction 1a is executed. When "occurrence of the interruption" is sent to the processor at this point of time, at timing t1, the address AAAA indicating the storage area for the instruction 2a, i.e., the instruction at the head of the procedure for interruption processing is obtained as the instruction address and the instruction 2a is executed. At timing t2, the instruction 2b subsequent to the instruction 2a is executed. The following instructions are sequentially executed and then at timing tk, the cause of the interruption is analyzed, and thereby the address at the head of the procedure for performing processing for the cause of the interruption is obtained. At timing tk+1, the instruction address XXXX is obtained and thereby the instruction 3a at the head of the procedure for performing processing for the cause of the interruption is executed.
In some cases, the computer system is extended by increasing peripheral devices or adding application programs. The extension of the system often results in an increased number of causes of the interruption. When the interruption occurs, the prior art general processor carries out the procedure for interruption processing which is stored in a fixed storage area to analyze the cause of the interruption, and then performs processing for the cause of the interruption. Therefore, if the causes of the interruption increase, they can be handled flexibly by adding the procedure for analyzing them and the procedure for performing processing for them.
However, the general processor always fetches and executes the instructions in the fixed procedure to analyze the cause of the interruption before it preforms processing for the cause of the interruption. The analysis process generally requires several steps, and thereby the interruption cannot be handled quickly. As a solution to this, some of the prior art processors perform interruption processing in the following way to realize high-speed processing.
FIG. 9 is a diagram for explaining a processor which performs high-speed processing according to the prior art, and showing an example of the above processors based on a manual of a microcontroller SH-3 manufactured by Hitachi Co. Turning to FIG. 9, the processor comprises a vector base register 901, an event register 902, and a main storage 903 which contains procedures for performing processing for respective causes of interruption. The vector base register 901 holds a vector base indicating a reference address. The event register 902 holds a cause of interruption when an interruption occurs. The main storage 903 contains interruption processing 1 for an "interruption cause 1", interruption processing 2 for an "interruption cause 2", . . .
In the prior art processor which performs high-speed processing, the procedure for each interruption processing is stored in an area starting at an address (address indicating a starting position of an area) calculated from a reference address and an offset value. To be specific, the procedure for interruption processing 1 is stored in an area starting at an address obtained by adding the reference address (base) and an offset value 1 (offset 1), and the procedure for interruption processing 2 is stored in an area starting at an address obtained by adding the reference address (base) and an offset value 2 (offset 2).
As the offset value, a vector offset value obtained by hardware as a result of an occurrence of the interruption is used. For instance, in a system which caches a set of a logical address and a physical address by the use of a translation look-aside buffer (TLB) which realizes a high-speed virtual storage management mechanism, when it is not hit in a cache, "0.times.00000400" indicating a TLB mistake is obtained. The address obtained by adding the value obtained as the offset value to the reference address (base) is used as the starting address, to perform the procedure for performing processing for the cache mistake.
When the interruption occurs in the above processor, the cause of the interruption obtained by hardware is stored in the event register 902. The processor adds the base value indicating the reference address held by the vector base register 901 to the vector offset value obtained from the interruption cause which is held by the event register 902, to obtain the starting address of interruption processing. Then, one of the interruption processing 1, 2, . . . for the cause of the interruption is performed.